Universal Verification Methodology

#	Item
11	DVCon-2012_What-is-new-in-SystemVerilog-2012.fm Add to Reading List Source URL: www.sutherland-hdl.com Language: English - Date: 2012-11-02 18:47:29 Hardware description languages SystemVerilog Verilog Universal Verification Methodology E SV Integrated circuit design Generic programming Type system Electronic engineering Hardware verification languages Electronic design automation
12	PDF Document Add to Reading List Source URL: www.duolog.com Language: English - Date: 2012-02-28 09:15:56 IP-XACT Electronic design automation Hardware verification languages Standards organizations Universal Verification Methodology Accellera E Hardware register Electronic engineering Electromagnetism Electrical engineering